EMMC Lifetime (AN50)

Affected Products	All congatec products with eMMC

Preface

This application note explains how to estimate, increase, and monitor eMMC lifetime.

Terminology

Term	Description
eMMC	Embedded Multi-Media Card
OTP	One Time Programmable
ECC	Error Correction Code
P/E	Program-Erase
SLC	Single Level Cell
MLC	Multi Level Cell
TLC	Triple Level Cell
QLC	Quadruple Level Cell
pSLC	Pseudo Single Level Cell

Introduction to eMMC Lifetime

Embedded Multi-Media Cards (eMMCs) are based on NAND flash. All NAND flash-based storage devices have a limited lifetime.

In simple terms, programming and erasing data gradually weakens a NAND flash cell until it can no longer properly hold a charge or differentiate between the voltage levels. This phenomenon limits the lifetime of an eMMC. A detailed explanation of this phenomenon is outside the scope of this application note.

Flash Controller

The flash controller is part of an eMMC. It improves the lifetime of the NAND flash via various features, such as:

Wear Leveling Repeated writes to the same memory cell eventually lead to the cell no longer being able to retain data. The wear leveling feature ensures that the data is distributed evenly.
Bad Block Management A bad block is a flash block that cannot be successfully written or erased without bit-errors. Information about existing bad blocks is stored on the device by the manufacturer. Additional bad blocks can develop over time. The flash controller recognizes them and adds them to the list of bad blocks. Future write/erase procedures can work around these bad blocks.
ECC Error correction code is used to identify and correct errors. This is typically achieved by adding a number of redundant bits to a data string. The encoded message can then be decoded by the controller to check for and correct bit errors in the message.
Garbage Collection If data within certain pages of a block is no longer needed, the controller can just read back and rewrite the necessary data to a previously erased empty block. The leftover pages can then be used for new data.

Flash Cell Types

eMMCs implement one main flash cell type. The different types can store different numbers of bits per cell. Flash cell types with a lower number of bits per cell can typically endure a significantly higher number of Program-Erase (P/E) cycles.

The table below compares the different flash cell types. Use the stated P/E cycles as a guideline only and request them from your FAE for a particular congatec product.

	SLC Single Level Cell	3D-MLC Multi Level Cell	3D-TLC Triple Level Cell	3D-QLC Quadrupel Level Cell
Bits/Cell	1	2	3	4
Density	Low	Mid	High	Highest
P/E Cycles	~100,000	~5,000	~3,000	~1,000

Note:

The flash cell types with planar (2D) or 3D NAND technology feature different P/E cycle values. 3D NAND flash increases capacity and reliability of an eMMC.

Caution:

The use-case of eMMCs should keep to the specified P/E cycle limits of their Flash Cell Types and the manufacturer's specification. Exceeding these P/E cycle limits can result in premature wear, significant reduction of lifetime, or even death of the eMMC. Please also compare and stick to what the manufacturer recommends in their guidelines.

Enhanced User Area and pSLC Mode

The JEDEC JESD84-B51 standard describes a storage mode, whereas all or parts of the eMMCs memory can be reconfigured to a more robust and reliable mode.

How the enhanced user area is implemented is up to the eMMC manufacturer.

For eMMCs that are used on congatec products, the enhanced user area is pseudo-SLC mode.

This mode greatly increases the maximum number of P/E cycles by reducing the bits per cell to one, same as SLC. That’s why this mode is called pseudo-SLC.

The trade-off is a greatly reduced storage capacity – it is divided by the bits per cell of the flash cell type (e.g., leaves 1/3 of the original storage capacity of an eMMC with TLC flash cell type).

To enable this mode, refer to section 3.2.

Note:

The enhanced user area mode for eMMCs on congatec products is pSLC.

Estimating the eMMC Lifetime

The amount of logic data that can be written to the eMMC until the end of its lifetime can be estimated with this formula:

TBW = DC * EF / WAF


TBW	Total Bytes Written throughout the lifetime of the eMMC.
DC	Device Capacity in bytes.
EF	Endurance Factor. Use the max. P/E cycles of the eMMC. Request it from your FAE for a particular congatec product.
WAF	Write Amplification Factor. Basically, NAND flash organizes data in groups. Data can only be programmed in groups (pages) and erased in groups of pages (blocks). A page can be several KB or even MB in size and a block can consist of hundreds of pages. This typically means that the actual amount of physical data written to the NAND flash is a factor of 8 to 20 times greater than the logic data written by the host. This phenomenon is called Write Amplification (WA). A more detailed description of this phenomenon is beyond the scope of this application note.

Divede the TBW by the average logic data written to estimate the lifetime in number of days.

Example

In this example, we estimate the lifetime of a conga-SA5/i-E3950-4G eMMC32 (Revision B.3). This module uses an eMMC with 3D TLC NAND flash technology that supports 3,000 P/E cycles. We assume an inefficient WAF of 20 for our specific use case.

Filling in these values into the previously mentioned formula gives us the following TBW:

TBW = 32 GB * 3,000 / 20 = 4.8 TB

If we assume that 1 GB of logic data is written to the eMMC on average per day, we can estimate the lifetime in days:

Lifetime = 4,8 TB / 1 GB / day = 4800 days or 13.15 years

Note:

Request the P/E cycle value from your FAE for a particular congatec product.

Increasing the eMMC Lifetime

The sections below provide some general guidelines and special procedures that can increase the lifetime of eMMCs. Section 3.2.1 describes prerequisites that apply to several procedures.

General Guidelines

The formula in section 2 introduced variables that influence the lifetime of all eMMC devices. Based on these variables, the following general guidelines can be deduced:

Use a congatec product with a larger device capacity (DC)
Decrease the amount of logic data Adjust applications to decrease the writing frequency and only writing necessary data. Outsource frequently changed data to a different medium whenever possible (i.e. logs).
Decrease the amount of physical data (WAF)

Adjust applications to write more efficient, bigger sequential writes to the eMMC instead of smaller randomized writes. The ideal size depends on the page sized. Another way is described in section "Enabling eMMC Cache"

Enabling Enhanced Mode (pSLC)

This section explains how to enable the enhanced mode. As explained is section "Enhanced User Area and pSLC Mode", the pSLC enhanced mode can be enabled on some eMMCs to greatly increases their lifetime at the expense of storage capacity.

Note:

The procedure was tested on Ubuntu 2.04.1 LTS with kernel 5.8.0-38-generic.

Prerequisites

Follow the instructions below to prepare for enbaling the pSLC mode:

Install a Linux based operating system on a medium that is not the target eMMC
Install mmc-utils

sudo apt-get install mmc-utils

List all available eMMC devices

dmesg | grep mmc Example console output: […] mmc1: new HS400 MMC card at address 0001 mmcblk1: mmc1:0001 M5232 28.5GiB

Identify your target eMMC disk name from the output (e.g. mmcblk1)
Ensure that the target eMMC is of standard 5.0 or higher with extended CSD register revision 1.7 or higher

sudo mmc extcsd read /dev/yourtargetdiskname | head -n 3

Example console output:

==========================================

Extended CSD rev 1.7 (MMC 5.0)

==========================================

Note:

Replace "yourtargetdiskname" with your target eMMC disk name in all commands.

If these two conditions are met, the pSLC mode can be enabled on the target eMMC.

Enabling Enhanced Mode (pSLC)

Caution:

The procedures described in this section erase all data on your target eMMC and permanently decrease its storage capacity. This procedure is non-reversible (OTP).

Note:

The procedure described in this section can also be used to enable pSLC on one or more partitions. The storage capacity of the other partitions is not reduced. This way, write-intensive tasks may be relocated to a pSLC partition while other partitions can keep their original (larger) storage capacity for less write-intensive tasks.

Replace "yourtargetdiskname" with your target eMMC disk name in all commands.

Follow the instructions below to enable the pSLC mode on the target eMMC.

The example console outputs refer to a setup with a 32GB 3D-MLC device.

Find the maximum size of the target eMMC disk after reconfiguring to pSLC mode:

sudo mmc extcsd read /dev/yourtargetdiskname | grep ENH_SIZE_MULT -A 1

Example console output:

Max Enhanced Area Size[MAX_ENH_SIZE_MULT]: 0x0001c8 i.e. 14942208 KiB

Set the enhanced attribute for the target partition to the size reported from the previous step

sudo mmc enh_area set -y 0 14942208 /dev/yourtargetdiskname

Perform a power cycle.

Confirm ENH_SIZE_MULT:

sudo mmc extcsd read /dev/yourtargetdiskname | grep ENH_SIZE_MULT -A 1

Check if the reported MAX_ENH_SIZE_MULT matches ENH_SIZE_MULT.

Confirm new size of the target partition with the size reported from step 1:

sudo fdisk -l /dev/yourtargetdiskname

Example console output:

Disk /dev/yourtargetdiskname : 14,26 GiB [...]

The pSLC mode is now enabled on your target eMMC.

Enabling eMMC Cache

eMMC cache decreases the WAF in case small blocks must be written and cannot be avoided by an application. The eMMC cache is usually turned on by default.

Follow the instructions below to check if the eMMC cache is enabled and, if necessary, to enable it:

Follow the instructions in section "Prerequisites" until step 4

Retrieve cache information from EXT_CSD register

sudo mmc extcsd read /dev/yourtargetdiskname | grep CACHE_CTRL

Example console output (0x00 means cache is OFF; 0x01 means cache is ON):

Control to turn the Cache ON/OFF [CACHE_CTRL]: 0x00

==========================================

Note:

Replace "yourtargetdiskname" with your target eMMC in all commands.

Enable eMMC Cache

sudo mmc cache enable /dev/yourtargetdiskname

Perform a Powe Cycle
Repeat step 2 to verify that the value is 0x01

The eMMC cache is enabled now.

eMMC maintenance

eMMC is able to perform so called Background Operations (BKOPS). It is an essential maintenance function that is performed to enhance the eMMC performance and lifespan. These operations reduce latencies during read and write processes, optimize NAND flash memory, and include tasks like wear leveling and managing bad blocks. Enabling BKOPS periodically is crucial, particularly for TLC-based eMMC, to prevent performance degradation and memory wear.

Note:

Not activating BKOPS can lead to data loss and severe performance problems.

Depending on the chip's default settings, background operations might or might not be executed periodically, affecting the worst-case read and write latency.

Conditions for good eMMC maintenance

To ensure reliable BKOPS operations, the eMMC needs periods of low activity from the host, allowing maintenance during free time. Enabling TRIM in your OS is essential, as it informs the eMMC controller which data blocks are no longer in use, optimizing garbage collection. A healthy NAND flash is also crucial; if the flash is heavily worn or has many bad blocks, BKOPS may be less effective, and replacing the eMMC might be necessary. Adequate free space on the device helps the controller optimize data layout efficiently. Background Operations are triggered when certain thresholds - like high program/erase cycles or used block percentages - are met. Enabling BKOPS_EN ensures these operations can be performed as needed, though improvements may take longer if the eMMC is fragmented or worn.

Enabling Background Operations in Linux

Caution:

The procedures described in this section can be done only once. This procedure is non-reversible (OTP).

In Windows and other operating systems, BKOPS settings are typically managed automatically by the device driver or eMMC firmware, offering limited options for user configuration. Windows emphasizes simplicity and user-friendliness by automating these processes, reducing the need for manual intervention. On the other hand, Linux provides users and system administrators with a higher degree of control and customization, including detailed management of hardware settings and operations like eMMC. This flexibility in Linux requires more expertise for effective management. Tools like mmc-utils can be used in Linux environments to interact with the eMMC and configure BKOPS.

JEDEC Standard 5.1 enables two different ways of enabling Background Operations:

Auto: a Host that wants to enable the device to perform background operations during device idle time automatically. If the setting of AUTO_EN in BKOPS_EN field [EXT_CSD byte 163] is set to 1b, the device may start or stop background operations whenever it sees fit, without any notification to the host.

mmc bkops_en auto /dev/yourtargetdiskname (for automatic configuration)

Manual: In order for the device to know when the host does not need it and it can execute background operations, host shall write any value to BKOPS_START (EXT_CSD byte [164]) to manually start background operations. Device will stay busy till no more background processing is needed. The Host should check if background operations are necessary.

mmc bkops_en manual /dev/ yourtargetdiskname (for manual configuration)

Afterwards you can check the configuration with

sudo mmc extcsd read /dev/yourtargetdiskname | grep BKOPS_SUPPORT

0x00	BKOPS is not supported
0x01	BKOPS is supported but not automatically enabled (= manual configuration)
0x02	BKOPS is supported and automatically enabled

and monitor the BKOPS Status with

sudo mmc extcsd read /dev/yourtargetdiskname | grep BKOPS_STATUS

0x0	No operations required
0x1	Operations outstanding (non critical)
0x2	Operations outstanding (performance being impacted)
0x3	Operations outstanding (critical)

Monitoring eMMC Health Status

Beginning with the JEDEC eMMC 5.0 standard, the Extended Card-Specific Data register features lifespan monitoring data.

Follow the instructions below to retrieve this data:

Follow the instructions in section "Prerequisites" until step 4
Retrieve lifespan information from the EXT_CSD register

sudo mmc extcsd read /dev/yourtargetdiskname | grep -A 1 LIFE

Example console output:

eMMC Life Time Estimation A [EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A]: 0x01
eMMC Life Time Estimation B [EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B]: 0x01
eMMC Pre EOL information [EXT_CSD_PRE_EOL_INFO]: 0x01

For DEVICE_LIFE_TIME_EXT_TYP_[A;B], eMMC manufacturers must adhere to a scheme where:

0x01 - 0%-10% of device lifetime is used
0x02 - 10%-20% of device lifetime used
… and so on in steps of 10%
0x0B - Lifetime of the device is exceeded

DEVICE_LIFE_TIME_EXT_TYP_A reports the lifespan data of flash cells that are in their base configuration.

DEVICE_LIFE_TIME_EXT_TYP_B reports the lifespan data of flash cells configured to enhanced mode (pSLC).

Note:

DEVICE_LIFE_TIME_TYP_B is always reported for eMMCs that feature the enhanced mode - even if an enhanced user area is not configured - because specific partitions are permanently configured to this mode. Refer to JEDEC standard JESD84_B51 for more information about default partitions.

For PRE_EOL_INFO, eMMC manufacturers must adhere to a scheme where:

0x01 - Normal: Consumed less than 80% of the reserved blocks
0x02 - Warning: Consumed 80% of the reserved blocks
0x03 - Urgent: Consumed 90% of the reserved blocks. Urgent end-of-life warning.

Caution:

The eMMC becomes read-only when 100% of the reserved blocks are consumed. New data will not be saved and may get lost.